Projects

VLSI PROJECTS

  • Efficient Energy-Efficient ECG Signal Processing using Pruned and Truncated Haar Discrete Wavelet Transform and Integer Wavelet Transform
  • Design of low power and low area 4-bit flash ADC using SAR comparator on CMOS process
  • Implementation of qam modulator and demodulator for 5G
  • VLSI implementations of high-speed adaptive filter structure for speech enhancement
  • Throughout area Optimized Architecture for Elliptic-Curve Diffie-Hellman protocols
  • COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC (RP)
  • A fully Differential Difference Transconduction Amplifier Topology based on memristor
  • Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function
  • Implementation of SVM-Based Low Power EEG Signal Classification Chip
  • A Single-Chip Solution for Diagnosing Peripheral Arterial Disease
  • Approximate Radix Booth Multipliers for Low-Power and High-Performance Operation
  • Design of High speed vedic multiplier
  • Low power array multiplier using modified full adder
  • Low Power and Area Efficient Carry Select Adder
  • Design of area and power efficient digital FIR filter for FPGA
  • Transient and permanent fault diagnosis TMR system on FPGA
  • High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications
  • Design an Energy Efficient Carry Speculative Adder
  • High performance redundant binary multiplier
  • FPGA implementation of low power digital QPSK modulator
  • Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers
  • Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations
  • Vlsi Implementation of Edge Detection for Images
  • Double precision floating-point arithmetic on FPGAs
  • High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder